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? semiconductor components industries, llc, 2014 january, 2014 ? rev. 0 1 publication order number: NCV4275C/d NCV4275C 450 ma low-drop voltage regulator with reset the NCV4275C is an integrated low dropout regulator designed for use in harsh automotive environments. it includes wide operating temperature and input voltage ranges. the output is regulated at 5.0 v or 3.3 v and is rated to 450 ma of output current. it also provides a number of features, including overcurrent protection, overtemperature protection and a programmable microprocessor reset. the NCV4275C is available in the dpak and d 2 pak surface mount packages. the output is stable over a wide output capacitance and esr range. the NCV4275C is pin for pin compatible with ncv4275a. features ? 5.0 v or 3.3 v 2% output voltage options ? 450 ma output current ? very low current consumption ? active reset output ? reset low down to v q = 1.0 v ? 500 mv (max) dropout voltage ? fault protection ? +45 v peak transient voltage ? ? 42 v reverse voltage ? short circuit protection ? thermal overload protection ? aec ? q100 qualified and ppap capable ? these are pb ? free devices applications ? auto body electronics + ? i d q gnd ro current limit and saturation sense bandgap reference thermal shutdown reset generator figure 1. block diagram error amplifier http://onsemi.com http://onsemi.com d 2 pak 5 ? pin ds suffix case 936a 1 5 dpak 5 ? pin dt suffix case 175aa ordering information 1 5 marking diagrams 1 1 x = 5 (5.0 v output) or 3 (3.3 v output) a = assembly location wl, l = wafer lot y = year ww = work week g = pb ? free package 4275cxg alyww nc v4275cx awlywwg see detailed ordering and shipping information on page 13 of sheet.
NCV4275C http://onsemi.com 2 pin function description pin no. symbol description dpak ? 5 d2pak ? 5 1 i input; battery supply input voltage. bypass to ground with a ceramic capacitor. 2 ro reset output; open collector active reset (accurate when i > 1.0 v). 3, tab gnd ground; pin 3 internally connected to tab. 4 d reset delay; timing capacitor to gnd for reset delay function. 5 q output; 2.0%, 450 ma output. bypass with 22 f capacitor, esr < 4.5 (5.0 v version), 3.5 (3.3 v version). maximum ratings rating symbol min max unit input v oltage v i ? 42 45 v input peak t ransient v oltage v i ? 45 v output v oltage v q ? 1.0 16 v reset outp ut voltage v ro ? 0.3 25 v reset output current i ro ? 5.0 5.0 ma reset delay voltage v d ? 0.3 7.0 v reset delay current i d ? 2.0 2.0 ma esd susceptibility (note 1) ? human body model ? machine model ? charge device model esd hbm esd mm esd cdm 4.0 200 1000 ? ? ? kv v v junction t emperature t j ? 40 150 c storage t emperature t stg ? 55 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. this device incorporates esd protection and is tested by the followign methods: esd human body model tested per aec ? q100 ? 002, esd machine model tested per aec ? q100 ? 003, esd charged device model tested per aec ? q100 ? 011, latch ? up tested per aec ? q100 ? 004. operating range rating symbol min max unit input v oltage operating range, 5.0 v output v i 5.5 42 v input voltage operating range, 3.3 v output v i 4.4 42 v junction t emperature t j ? 40 150 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond th e recommended operating ranges limits may affect device reliability. lead temperature soldering reflow and msl (note 2) rating symbol min max unit lead free, 60 sec ? 150 sec above 217 c t sld ? 265 peak c moisture sensitivity level msl 1
NCV4275C http://onsemi.com 3 thermal characteristics characteristic test conditions (typical v alue) unit dpak 5 ? pin p ackage min pad board (note 3) 1 in pad board (note 4) junction ? to ? tab (r jt ) 5.1 5.5 c/w junction ? to ? ambient (r ja ) 82.4 58.1 c/w d 2 pak 5 ? pin p ackage 0.4 sq. in. spreader board (note 5) 1.2 sq. in. spreader board (note 6) junction ? to ? tab (r jt ) 4.5 4.8 c/w junction ? to ? ambient (r ja ) 66.0 49.0 c/w 2. pr r ipc / jedec j ? std ? 020c 3. 1 oz. copper, 0.26 inch 2 (168 mm 2 ) copper area, 0.062 thick fr4. 4. 1 oz. copper, 1.14 inch 2 (736 mm 2 ) copper area, 0.062 thick fr4. 5. 1 oz. copper, 0.373 inch 2 (241 mm 2 ) copper area, 0.062 thick fr4. 6. 1 oz. copper, 1.222 inch 2 (788 mm 2 ) copper area, 0.062 thick fr4.
NCV4275C http://onsemi.com 4 electrical characteristics (v i = 13.5 v; ? 40 c < t j < 150 c; unless otherwise noted.) characteristic symbol test conditions min typ max unit output output v oltage v q 100 a i q 400 ma 6.0 v v i 28 v (5.0 v version) 4.4 v v i 28 v (3.3 v version) 4.9 3.23 (2%) 5.0 3.3 5.1 3.37 (2%) v output v oltage v q 100 a i q 200 ma 6.0 v v i 40 v (5.0 v version) 4.4 v v i 40 v (3.3 v version) 4.9 3.23 (2%) 5.0 3.3 5.1 3.37 (2%) v output current limitation i q v q = 0.9 x v q,typ 450 650 ? ma quiescent current i q = i i ? i q i q i q = 1.0 ma, t j = 25 c ? 135 150 a i q = 1.0 ma ? 150 200 a i q = 250 ma ? 10 15 ma i q = 400 ma ? 23 35 ma dropout voltage (note 7) v dr i q = 300 ma v dr = v i ? v q ? 250 500 mv load regulation v q i q = 5.0 ma to 400 ma ? 30 15 30 mv line regulation v q v i = 8.0 v to 32 v, i q = 5.0 ma ? 15 5.0 15 mv power supply ripple rejection psrr f r = 100 hz, v r = 0.5 v pp ? 60 ? db temperature output v oltage drift dv q /dt ?? ? 0.5 ? mv/k reset timing d and output ro reset switching threshold 5.0 v version 3.3 v version v q,rt v out decreasing v in > 5.5 v v in > 4.4 v 90 90 93 93 96 96 % v out reset output low voltage v rol r ext 5.0 k , v q 1.0 v ? 0.2 0.4 v reset output leakage current i roh v roh = 5.0 v ? 0 10 a reset charging current i d,c v d = 1.0 v 3.0 5.5 9.0 a upper timing threshold v du ?? 1.5 1.8 2.2 v lower timing threshold v dl ?? 0.2 0.4 0.7 v reset delay time t rd c d = 47 nf 10 16 22 ms reset reaction time t rr c d = 47 nf ? 1.5 4.0 s thermal shutdown shutdown temperature (note 8) t sd ?? 150 ? 210 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. only for 5 v version. measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v. 8. guaranteed by design, not tested in production.
NCV4275C http://onsemi.com 5 typical performance characteristics 3.26 3.28 3.3 3.32 3.34 3.36 ? 40 ? 20 0 20 40 60 80 100 120 140 160 figure 2. output stability with output capacitor esr figure 3. output stability with output capacitor esr figure 4. output stability with output capacitor esr figure 5. output stability with output capacitor esr figure 6. output voltage v q vs. temperature t j figure 7. output voltage v q vs. temperature t j 0.01 0.1 1 10 i q , output current (ma) esr ( ) c q = 22 f stable esr region 0 100 200 300 400 v q(nom) = 5.0 v c q = 22 f stable esr region 0 100 200 300 400 v q(nom) = 3.3 v 0.01 0.1 1 10 i q , output current (ma) esr ( ) 0.1 1 10 100 0.01 i q , output current (ma) esr ( ) c q = 1 f stable esr region 0 100 200 300 400 v q(nom) = 5.0 v 0.1 1 10 100 i q , output current (ma) esr ( ) c q = 1 f stable esr region 0 100 200 300 400 v q(nom) = 3.3 v v q , output volage (v) t j , junction temperature ( c) v in = 13.5 v, i out = 200 ma v q(nom) = 5.0 v v q , output volage (v) t j , junction temperature ( c) v q(nom) = 3.3 v 5.0 v version 3.3 v version 4.90 4.93 4.95 4.98 5.00 5.03 5.05 5.08 5.10 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v in = 13.5 v, i out = 200 ma
NCV4275C http://onsemi.com 6 typical performance characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0246810 figure 8. output voltage v q vs. input voltage v in figure 9. output voltage v q vs. input voltage v in figure 10. output current i q vs. temperature t j figure 11. output current i q vs. temperature t j figure 12. output current i q vs. input voltage v in figure 13. output current i q vs. input voltage v in v q , output voltage (v) v in , input voltage (v) v q(nom) = 5.0 v v q , output voltage (v) v in , input voltage (v) v q(nom) = 3.3 v i q , output current limitation (a) t j , junction temperature ( c) i q , output current limitation (a) t j , junction temperature ( c) i lim , i sc , current limit (ma) v in , input voltage (v) ii lim , i sc , current limit (ma) v i , input voltage (v) 5.0 v version 3.3 v version 0 1 2 3 4 5 6 0246810 i out = 200 ma t j = 25 c i out = 200 ma t j = 25 c 500 550 600 650 700 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v in = 13.5 v v q(nom) = 5.0 v 500 550 600 650 700 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v in = 13.5 v v q(nom) = 3.3 v 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 35 40 v q(nom) = 5.0 v t j = 25 c t j = 125 c 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 35 40 t j = 25 c t j = 125 c v q(nom) = 3.3 v
NCV4275C http://onsemi.com 7 typical performance characteristics figure 14. current consumption i q vs. output current i q figure 15. current consumption i q vs. output current i q i q , current consumption (ma) i q , output current (ma) v in = 13.5 v, t j = 25 c figure 16. current consumption i q vs. output current i q figure 17. current consumption i q vs. output current i q figure 18. charge current i d,c vs. temperature t j figure 19. delay switching threshold v du , v dl vs. temperature t j v q(nom) = 5.0 v i q , current consumption (ma) i q , output current (ma) v q(nom) = 5.0 v i dc , charge current ( a) t j , junction temperature ( c) i q , current consumption (ma) i q , output current (ma) v q(nom) = 3.3 v i q , current consumption (ma) i q , output current (ma) i dc , charge current ( a) t j , junction temperature ( c) 0 0.5 1 1.5 2 2.5 3 0 20406080100120 0 0.5 1 1.5 2 2.5 3 0 20 40 60 80 100 120 v in = 13.5 v, t j = 25 c 0 5 10 15 20 25 30 0 50 100 150 200 250 300 350 400 450 v in = 13.5 v, t j = 25 c 0 5 10 15 20 25 30 0 50 100 150 200 250 300 350 400 450 v q(nom) = 3.3 v v in = 13.5 v, t j = 25 c 0 1 2 3 4 5 6 7 8 9 10 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v in = 13.5 v, v d = 1 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2 2.2 ? 40 ? 20 0 20 40 60 80 100 120 140 160 1.6 1.8 v in = 13.5 v
NCV4275C http://onsemi.com 8 typical performance characteristics 0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 figure 20. drop voltage v dr vs. output current i q v dr , dropout voltage (mv) i q , output current (ma) t j = 125 c v q(nom) = 5.0 v t j = 25 c
NCV4275C http://onsemi.com 9 application information v i c i1 1000 f c i2 100 nf c d 47 nf i i i d i d 1 4 5 2 3 gnd c q 22 f i ro i q q ro r ext 5.0 k v q v ro figure 21. test circuit NCV4275C i q circuit description the NCV4275C is an integrated low dropout regulator that provides 5.0 v or 3.3 v, 450 ma protected output and a signal for power on reset. the regulation is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. the output current capability is 450 ma, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. the delay time for the reset output is adjustable by selection of the timing capacitor. see figure 21, test circuit, for circuit element nomenclature illustration. regulator the error amplifier compares the reference voltage to a sample of the output voltage (v q ) and drives the base of a pnp series pass transistor by a buffer. the reference is a bandgap design to give it a temperature ? stable output. saturation control of the pnp is a function of the load current and input voltage. over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. regulator stability considerations the input capacitors (c i1 and c i2 ) are necessary to stabilize the input impedance to avoid voltage line influences. using a resistor of approximately 1.0 in series with c i2 can stop potential oscillations caused by stray inductance and capacitance. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum, aluminum or ceramic capacitors can be used. the range of stability versus capacitance, load current and capacitive esr is illustrated in figures 2 to 5. minimum esr for c q = 22 f is native esr of ceramic capacitors. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the capacitance and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 21, test circuit, should work for most applications; however, it is not necessarily the optimized solution. stability is guaranteed for c q 22 f and an esr 4.5 (5.0 v version), 3.5 (3.3 v v ersion). esr characteristics were measured with ceramic capacitors and additional resistors to emulate esr. murata ceramic capacitors were used, grm32er71a226me20 (22 f, 10 v, x7r, 1210), grm31mr71e105ka01 (1 f, 25 v, x7r, 1206). reset output the reset output is used as the power on indicator to the microcontroller. this signal indicates when the output voltage is suitable for reliable operation of the controller. it pulls low when the output is not considered to be ready. ro is pulled up to v q by an external resistor, typically 5.0 k in value. the input and output conditions that control the reset output and the relative timing are illustrated in figure 22, reset timing. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0.0 v to the upper timing threshold vol tage v du . the charging current for this is i d,c and d pin voltage in steady state is typically 2.4 v. by using typical ic parameters with a 47 nf capacitor on the d pin, the following time delay for 5.0 v regulator is derived: t rd = c d v du / i d,c t rd = 47 nf (1.8 v) / 5.5 a = 15.4 ms other time delays can be obtained by changing the capacitor value.
NCV4275C http://onsemi.com 10 figure 22. reset timing v i v q v d v ro reset delay time reset reaction time power ? on ? reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output < reset reaction time t t t t v q,rt upper timing threshold v du lower timing threshold v dl dv d dt reset charge current c d
NCV4275C http://onsemi.com 11 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 23) is: p d(max) [v i(max) v q(min) ]i q(max) (1) v i(max) i q where v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i q i i figure 23. single output regulator with key performance parameters labeled v i v q } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where r jc is the junction ? to ? case thermal resistance, r cs is the case ? to ? heatsink thermal resistance, r sa is the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d. 40 60 80 100 120 140 0 100 200 300 400 500 600 700 800 40 60 80 100 120 140 160 0 100 200 300 400 500 600 700 800 figure 24. ja vs. copper spreader area, dpak 5 ? lead figure 25. ja vs. copper spreader area, d 2 pak 5 ? lead copper area spreader area (mm 2 ) r ja, thermal resistance (c /w) dpak 2 oz dpak 1 oz copper area spreader area (mm 2 ) r ja, thermal resistance (c /w) d2pak 2 oz d2pak 1 oz
NCV4275C http://onsemi.com 12 time (sec) r(t) c /w cu area 167 mm 2 cu area 736 mm 2 figure 26. single ? pulse heating curves, dpak 5 ? lead pulse time (sec) r(t) c /w cu area 167 mm 2 cu area 736 mm 2 figure 27. single ? pulse heating curves, d 2 pak 5 ? lead 0.1 1 10 100 0.000001 0. 00001 0.0001 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
NCV4275C http://onsemi.com 13 100 10 1.0 0.1 0.01 pulse width (sec) r ja 788 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non ? normalized response 50% duty cycle 20% 10% 5% 2% 1% 100 10 1.0 0.1 0.01 pulse width (sec) r ja 736 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non ? normalized response 50% duty cycle figure 28. duty cycle for 1? spreader boards, dpak 5 ? lead 20% 10% 5% 2% 1% figure 29. duty cycle for 1? spreader boards, d 2 pak 5 ? lead ordering information device output v oltage package shipping ? NCV4275Cds50r4g 5.0 v d2pak (pb ? free) 800 / tape & reel NCV4275Cdt50rkg dpak (pb ? free) 2500 / tape & reel NCV4275Cds33r4g 3.3 v d2pak (pb ? free) 800 / tape & reel NCV4275Cdt33rkg dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications,including part orientation and tape sizes, please refer to our tape and reel p ackaging specifications brochure, brd801 1/d.
NCV4275C http://onsemi.com 14 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 dpak 5, center lead crop dt suffix case 175aa issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
NCV4275C http://onsemi.com 15 package dimensions d 2 pak, 5 lead ds suffix case 936a ? 02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1 mm inches soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. sc illc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data she ets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for e ach customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designe d, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such u nintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this l iterature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV4275C/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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